1. Field of the Invention
The present invention relates to a test key and particularly to a test key and method for validating the position of a word line structure overlaying the deep trench capacitor in a DRAM.
2. Description of the Prior Art
The essential charge storage devices in a DRAM (Dynamic Random Access Memory) are frequently implemented by trench capacitors. The trench capacitor is formed in the substrate and has a capacitance proportional to the depth of the trench. That is to say, by increasing the depth of the trench, which results in a larger surface area of the “plates”, the trench capacitor provides a higher capacitance.
FIG. 1 is a diagram showing the layout of a conventional DRAM. A trench capacitor 10 is disposed beneath the passing word line. A transistor 14 is coupled to a node 16 of the trench capacitor 10 through a diffusion region 18. A diffusion region 20 is coupled to a plug 22. The plug 22 is coupled to a bit line (not shown). Thus, data is read from or written into the trench capacitor 10 through the node 16 by operation of the transistor 14. The transistor 14 is controlled by voltages on the word line 12. When a high voltage level is on the word line 12, a conductive channel is formed below the word line 12 so that a current flows from or to the node 16 through the diffusion regions 18 and 20, whereby the data is read from or written into the capacitor 10.
FIG. 2 shows a cross section along the line AA in FIG. 1. An STI (Shallow Trench Isolation) 28 is formed in the substrate and trench capacitor to define an active area and isolate the trench capacitor 10 from the word line 12 formed later. After formation of the word line 12, the diffusion regions 18 and 20, used as a source and drain, on two sides of the word line 12 are formed by ion implantation with masking of the word line 12 and STI 28. Thus, the position of the word line 12 overlaying the trench capacitor 10 has great impact on the profiles of the source and drain. For the DRAM having trench capacitors used as storage devices, an improper overlay of the word line and capacitor results in current leakage between adjacent memory cells or even defective cells. Validating the position of the word line is an essential step for DRAM manufacturing.